1. Field of the Invention
The invention relates in general to a method for programming a multi-level cell (MLC) memory, and more particularly to a method for programming a MLC memory which can have a better tightened program distribution in a read operation.
2. Description of the Related Art
FIGS. 1A˜1D are respectively schematic diagrams of threshold voltage (Vt) distributions of the programmed bits for a targeted programmed state in a conventional programming process of a MLC memory. As shown in FIG. 1A, the memory has an erase-state Vt distribution at first and each bit of the memory is to be programmed to a targeted programmed state. The Vt distribution of the targeted programmed state has a program verify (PV) level (a lower boundary). In order to have tightened Vt distribution of the programmed bits, a pre-PV level for the targeted programmed state is set to be lower than the PV level and two steps of program operations are performed as below.
In the first rough program operation, after a number of program shots, the bits of the memory are programmed to have a Vt distribution A as shown in FIG. 1B, some of which have a Vt level not lower than the pre-PV level of the targeted programmed state as shown by a dotted-line region in FIG. 1B. At the time, the memory records the bits passing (with a Vt level not lower than) the pre-PV level. Then, the bits with a Vt level lower than the pre-PV level in the Vt distribution A are further programmed to pass the pre-PV level to generate a new Vt distribution B as shown in FIG. 1C.
All the bits of the Vt distribution B pass the pre-PV level, and the memory records the bits passing the PV level first as shown by a dotted-line region in FIG. 1C. Following that, in the second fine program operation, the bits with a Vt level lower than the PV level in the Vt distribution B are further programmed to pass the PV level to generate the target program distribution C as shown in FIG. 1D and complete the whole programming process.
However, as shown in FIG. 1C, after the first program operation, some faster bits with a Vt level lower than and close to the PV level (denoted by a dotted-line region F) will be programmed again in the second program operation, which results in a widened Vt distribution for the target programmed state and in turn increases a bit error rate.